1. Field of the Invention
The present invention concerns high speed memory arrays. More specifically, the invention concerns reading contents and writing to a portion of a memory array during the same clock cycle without performing another decode operation, depending on the contents of the portion.
2. Related Art
Speed of access to memory is a critical performance factor for high speed microprocessors. Reading a cache memory is faster than writing, because when writing to a cache memory location, the location must first be found by reading an address tag before writing to the location. Therefore it is particularly important to improve speed of access to cache memory for write operations. One way this is conventionally done is by xe2x80x9cpipeliningxe2x80x9d writes, according to which during a first cycle a tag is read in a first pipeline stage for a first data location, and during a second cycle a second tag is read in the first stage for a second data location while the write operation to the first data location is performed in the second pipeline stage. Subsequently, a write operation may occur each cycle, since for each cycle a tag is read in the first stage and data is written in the second stage.
One limitation to this technique for improving write cycle time arises with sequential writes to a same data location. This does not tend to happen often in many applications, but it still presents an issue. Furthermore, at least in the context of xe2x80x9ctag arraysxe2x80x9d it tends to be more frequent, and thus more problematic.
Tag arrays are memories employed for address translation because a factor which slows cache access time concerns the translation which must occur between virtual addresses used by processes executing on the processor and the corresponding physical addresses of the processing system main memory. To improve access time for a cache, virtual addressing may be used for the cache. This in turn gives rise to using a tag array for certain aspects of cache access. Due to the nature of this application, for tag array memories there tends to be more frequent occurrence of sequential writes to a single location.
In one conventional way of handling an operation such as this, where a read must precede a write, the wordline for a selected line is held up for the full time of both the read and the write portions of the operation. This can present cycle time problems, according to which another interval is needed to restore bit lines. In one conventional alternative a multiport cell array is used, according to which one port is used for reading and another is used for writing, however, this has conventionally introduced the complication of a second decoder to enable the write wordline separate from the read wordline.
Thus there is a need to improve speed of memory write operations, including clear operations. Furthermore, the need is particularly acute in the context of memory arrays used for address tag arrays.
The present invention addresses the foregoing need as follows. In a first form, a method embodiment for selectively writing to a line in a memory array, includes the step of selecting a line in the memory array responsive to a first clock signal (clock xe2x80x9cC2xe2x80x9d) being asserted. Then the contents of the selected line is compared to a value. The line is written to selectively. That is, if the contents matches the value, the line is written responsive to a second clock signal (clock xe2x80x9cC1xe2x80x9d) being asserted. This writing occurs after the first clock signal is deasserted, and before the next time the first clock signal is asserted.
In another aspect, the step of selecting the line includes asserting an address signal to an address decoder during an interval when the first clock signal is asserted, and asserting a wordline signal for the line in the memory array responsive to decoding the address.
In a further aspect, the step of selectively writing to the line includes writing responsive to a xe2x80x9cwrite wordlinexe2x80x9d signal being asserted for the line. In an embodiment, asserting the write wordline signal includes, first deasserting the wordline signal responsive to the first clock signal being deasserted. The asserting of the write wordline signal is triggered responsive to the wordline transitioning from being asserted to being not asserted. Further, the write wordline signal is held asserted until the second clock signal is deasserted.
In another aspect, it should be noted that the write wordline is asserted without any extra decoding, that is, without any decoding in addition to the wordline and column decoding.
In another aspect, the step of selectively writing includes asserting a compare match signal responsive to the contents matching the value while C1 is asserted, and writing responsive to the compare match and write wordline signals.
In one embodiment the memory array is folded. That is, the array has at least first and second columns of bit lines. In this embodiment the method includes asserting a column select signal responsive to decoding the address, and, in another aspect, includes asserting a xe2x80x9cwrite columnxe2x80x9d signal for the line. The writing is thus responsive to the write column signal.
In an aspect, asserting the write column signal includes first deasserting the column select signal responsive to the first clock signal being deasserted. Then the asserting of the write column signal is triggered responsive to the compare match signal and to column select signal being asserted Further, the write column signal is held asserted until the second clock signal is deasserted.
In another form, an apparatus embodiment includes a memory array with lines of memory cells. The lines are coupled to respective wordlines. The lines may be selected by a wordline signal that is asserted responsive to the first clock signal, as described above. The apparatus also includes xe2x80x9cwrite wordlinexe2x80x9d generators coupled to respective wordlines. The apparatus further includes a comparator, which has a first set of inputs coupled to bit lines of the memory cells for reading the contents of the cells, and a second set of inputs for reading a value. The comparator has a compare match output upon which it asserts a compare match signal if the contents matches the value. In response to the compare match and write wordline signals, a write operation occurs for the line.
In a further aspect, the apparatus includes an address decoder coupled to the wordlines and to address lines. The address decoder is operable to assert a signal on one of the wordlines responsive to an address being asserted on the address lines.
In another aspect, according to one embodiment the write wordline generator includes first combinational logic circuitry, which has first and second input nodes coupled respectively to the second clock signal and one of the wordlines. This logic circuitry has an output node on which it asserts a voltage responsive to the clock signal and the wordline signal.
In yet another aspect, the write wordline generator includes latch circuitry, which has an input node coupled to the first combinational logic circuitry output node. The latch circuitry has an output node on which it asserts an output voltage. This output is asserted responsive to the first combinational logic circuitry output being asserted. Further, the latch holds the asserted latch output until the second clock signal is deasserted.
In yet another aspect, the write wordline generator includes final stage circuitry, which has first and second input nodes coupled respectively to the wordline and the latch circuitry output node. The final stage circuitry also has an output node on which it asserts a voltage responsive to the wordline signal and the first latch circuitry output being asserted.
In one embodiment the memory array array is folded, and therefore has at least first and second columns of bit lines. According to this embodiment, the address decoder has a column select output on which it asserts a column select signal responsive to the address asserted on the address lines.
In a further aspect of the folded array embodiment, the apparatus includes xe2x80x9cwrite columnxe2x80x9d generators for the respective columns. The write column generators are coupled to the compare match output and the column select output. A write column generator will assert a write column signal responsive to the compare match signal and the column select signal in order to write to the line selected by one of the wordline signals and the column selected by the column select signal.
According to another aspect, such a write column generator includes second combinational logic circuitry, which has first and second input nodes coupled respectively to the second clock signal and the column select output. This second combinational logic circuitry has an output node on which it will assert a voltage responsive to the clock signal and the column select signal.
Further, such a write column generator includes, in another aspect, second latch circuitry, which has an input node coupled to the second combinational logic circuitry output node. The second latch circuitry has an output node on which it will assert an output voltage. The asserting of the output is triggered responsive to the second combinational circuitry output being asserted. Once asserted, the second latch holds its output until the second clock signal is deasserted.
In a further aspect, the write wordline generator includes second final stage circuitry, which has first and second input nodes coupled to the compare match output and to the second latch circuitry output node. The second final stage circuitry has an output node on which it will assert a voltage responsive to the compare match signal and the second latch circuitry output being asserted.
In one embodiment, the writing is merely to clear a valid bit for the selected line. However, in other embodiments, the writing is not necessarily limited to just clearing a single bit. Also, in this embodiment by doing a clear, the write column can only reset the value of the cell. In other embodiments, the cell could be written with a dual rail write column enabling a true write to occur, i.e. either a one or a zero could be written to the memory cell.
From the foregoing, it should be appreciated it is advantageous that when a line is selected by the wordline at the beginning of a cycle of the first clock responsive to the first clock signal being asserted, if a tag match is detected for the line and the clear, or more generally the write operation, is therefore selected to occur for the line, the write will occur during the same cycle of the first clock. Moreover, this is achieved with a single decoder for multiport memory cells. That is, the memory cells include one port which has a bit line pair for reading (or writing), in the present context, and a special port with a single bit line for clearing, so that in the same clock cycle that the standard bit line pair reads the cell, the cell may be cleared with the special, single bit line while the standard bit line pair is being restored.